A TLB is a fairly standard part of micro-processor memory management
hardware. It's basically an address-translation cache, it caches the
n most-recently used (or algorithm of the day) address translations
to save having to look them up in the page tables, which can require
several memory accesses just to find a translation.
Even if cisco isn't using virtual memory on their on-board microprocessors,
there's usually still quite a bit of start-up ritual for some risc chips
and there may be some memory mapping needed just to make things addressable,
even if it's just a single map entry putting all of memory in one block
at a fixed address.
Did you really want to know. 8-)
George
> From: "Kevin Gannon" <kevin@gannons.net>
> To: "Scott Whyte" <swhyte@cisco.com>
> Cc: "Cisco NSP List" <cisco-nsp@puck.nether.net>
> References: <Pine.LNX.4.21.0010181548260.948-100000@garbo.cisco.com>
> Subject: Re: [nsp] GSR TLB ???
> Date: Thu, 19 Oct 2000 10:07:42 +0100
>
> Scott
> Thanks for that as a matter of interedt what does it do ??
>
> Purely curious we havent hit a problem otherwise I would
> be talking to the TAC. One of those over coffee things.
>
> Thanks & Regards,
> Kevin
> ----- Original Message -----
> From: Scott Whyte <swhyte@cisco.com>
> To: Erik L. Montemer <montemer@more.net>
> Cc: Cisco NSP List <cisco-nsp@puck.nether.net>
> Sent: Wednesday, October 18, 2000 11:49 PM
> Subject: RE: [nsp] GSR TLB ???
>
>
> >
> >
> > It Translation Lookaside Buffer initialization.
> >
> >
> > On Wed, 18 Oct 2000, Erik L. Montemer wrote:
> >
> > > my bad... before the microcode is downloaded to the LC
> > >
> > > --erik
> > >
> > > -----Original Message-----
> > > From: Erik L. Montemer [mailto:montemer@more.net]
> > > Sent: Wednesday, October 18, 2000 15:39
> > > To: Cisco NSP List
> > > Subject: RE: [nsp] GSR TLB ???
> > >
> > >
> > > TLB i believe is the boot loader for the line cards in the GSR, right
> before
> > > the microcode boots.
> > >
> > > --erik
> > >
> > > -----Original Message-----
> > > From: Eric Osborne [mailto:eosborne@cisco.com]
> > > Sent: Wednesday, October 18, 2000 14:28
> > > To: Deepak Jain
> > > Cc: Kevin Gannon; Aaron Weintraub; Cisco NSP List
> > > Subject: Re: [nsp] GSR TLB ???
> > >
> > >
> > > > TransLation Bridge?
> > > >
> > > > Part of the SONET start-up sequence if I am not very much mistaken.
> > > >
> > >
> > > I couldn't find anywhere where we print a message remotely like 'TLB
> > > INIT'. What's 'sh diag <slot>' look like, and what code are you on?
> > >
> > > I very much doubt it's a SONET thing. I have no idea if 'TLB' is a
> > > SONET state or not, but I bet that if 'TLB' really means anything,
> > > it's setting up the TLB on the LC CPU, or something along those
> > > lines.
> > >
> > >
> > >
> > > eric
> > >
> >
> > -Scott
> >
> > --
> > Scott Whyte swhyte@cisco.com | Hobbes: "What would *you* call the
> > Global Solutions Engineering | creation of the universe?"
> > Network Design Consultant |
> > CCIE 3340 | Calvin: "The Horrendous Space
> Kablooie!"
> >
> >
>
>
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