Re: [nsp] c7200 architecture question?

From: Siva Valliappan (svalliap@cisco.com)
Date: Fri Jun 08 2001 - 18:17:33 EDT


some comments inline.

cheers
.siva

On Fri, 8 Jun 2001, George Robbins wrote:

> The question is really how isolated the IO controlelr bus is, whether
> it's just a logical designation used on the IOC card, which simply plugs
> into one of the two busses available on the mid-plane metal-to-metal,
> or whether it's "bridged" via a PCI chipset.
>
> In the first case, you have only two busses.
>
> In the second case you have three busses, but one of them is subsidary
> to the main busses.
>
> What's interesting is really the distribution of function/connection
> beween the PA's, midplane and IOC and NSP/NSE slots, both what is and
> what was orginally architechted. Then contrase to the other PCI/PA
> implementaions on for gnerations of VIP's, the 7100's vs. the 2600/3600
> PCI...
>
> There are dual-wide PA's that use only one PCI bus, can select the
> least-used (CT3PA?), or use both (GEIP+). What color smoke comes
> out when you plug the "PA" on the GEIP+ into a VXR?

the PA from the GEIP+ is not supported on the 7200. never tried it myself
so i don't know what color of smoke will come out since i never connected
this together myself.

if you need higher performance GIGE on the 7200 (greater then the PA-GE)
i would suggest using the GIGE based IO controllers that can have up to
2x the performance of the GIGE PA in a 7200.

>
> George
>
> > From: Gert Doering <gert@greenie.muc.de>
> > To: Aaron Weintraub <aaronw@distracted.org>, cisco-nsp@puck.nether.net
> > Subject: Re: [nsp] c7200 architecture question?
> > References: <20010608223957.A22709@greenie.muc.de> <20010608165602.A24668@ivore.vger.com>
> >
> > Hi,
> >
> > (I take the liberty to bring cisco-nps back on CC:)
> >
> > On Fri, Jun 08, 2001 at 04:56:02PM -0400, Aaron Weintraub wrote:
> > > http://www.cisco.com/univercd/cc/td/doc/product/core/7206/port_adp/3471pac6.htm
> > >
> > > agrees with what you think, which also agrees with what I think.
> > >
> > > There are not 3 busses in the 720x to my knowledge.
> >
> > Actually, that document backs *both* statements :-)
> >
> > Quote: "The optional ports on the I/O controllers connect to a third PCI
> > bus, mb0, that connects to one of the PCI buses or to both of the PCI buses,
> > depending on which network processing engine (NPE) or network services
> > engine (NSE) is installed and supported in your system."
> >
> > So it's a separate bus, but the bandwidth used will usually be charged to
> > the other bus(es).
> >
> > Now the interesting question is: for which NPE/NSE, where does it connect
> > to? Even more fascinating :-) - but it seems that all available NPE/NSEs
> > connect mb0 to mb1.
> >
> > Quote: "For a Cisco 7200 VXR router that has an NPE-300, NPE-400, or NSE-1
> > installed, the following error messages are displayed:
> > %C7200-3-PACONFIG:Exceeds 600 bandwidth points for slots 0, 1, 3 & 5"
> >
> > (and similar for the lesser NPEs).
> >
> > So the book is in error (kind of). There are a few more (it claims the
> > NPE-300 runs with 300MHz, but the NPE itself claims 262 MHz), but the part
> > on IOS architecture (what it's about after all) seems to be very good.
> >
> > gert
> > --
> > USENET is *not* the non-clickable part of WWW!
> > //www.muc.de/~gert/
> > Gert Doering - Munich, Germany gert@greenie.muc.de
> > fax: +49-89-35655025 gert.doering@physik.tu-muenchen.de
>



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