Re: [nsp] c7200 architecture question?

From: Gert Doering (gert@greenie.muc.de)
Date: Fri Jun 08 2001 - 18:39:05 EDT


Hi,

On Fri, Jun 08, 2001 at 03:14:15PM -0700, Siva Valliappan wrote:
> > Quote: "The optional ports on the I/O controllers connect to a third PCI
> > bus, mb0, that connects to one of the PCI buses or to both of the PCI buses,
> > depending on which network processing engine (NPE) or network services
> > engine (NSE) is installed and supported in your system."
> >
>
> mb0 connects to mb1. so you effectively only have 2 PCI buses - mb1
> and mb2.

Thanks. This *is* unclear in the book, but the online docs boil down
to this (although the part about "or to both of the PCI buses" is
"interesting").

Bad luck, I had hoped that some of my bandwidth issues would disappear
overnight :-)

regards,

gert

-- 
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Gert Doering - Munich, Germany                             gert@greenie.muc.de
fax: +49-89-35655025                        gert.doering@physik.tu-muenchen.de



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