[c-nsp] MLPPP errors

[Michael Malitsky]

Hello,

Looking for help with an MLPPP bundle - 2xT1, terminating on a
7206/PA-8T-V35 with an external Adtran CSU/DSU bank.  The multilink
interface shows input framing errors for every input packet:

router#sh int mu1
Multilink1 is up, line protocol is up
  Hardware is multilink group interface
  Internet address is <local IP>
  MTU 1500 bytes, BW 3088 Kbit, DLY 100000 usec,
     reliability 129/255, txload 60/255, rxload 12/255
  Encapsulation PPP, LCP Open, multilink Open
  Open: IPCP, loopback not set
  Keepalive set (10 sec)
  DTR is pulsed for 2 seconds on reset
  Last input 00:00:00, output never, output hang never
  Last clearing of "show interface" counters 2d13h
  Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0
  Queueing strategy: weighted fair
  Output queue: 0/1000/4096/0 (size/max total/threshold/drops)
     Conversations  0/48/512 (active/max active/max total)
     Reserved Conversations 0/0 (allocated/max allocated)
     Available Bandwidth 2316 kilobits/sec
  5 minute input rate 151000 bits/sec, 95 packets/sec
  5 minute output rate 730000 bits/sec, 110 packets/sec
     9818128 packets input, 1970935965 bytes, 0 no buffer
     Received 0 broadcasts, 0 runts, 0 giants, 0 throttles
     9818297 input errors, 0 CRC, 9818282 frame, 15 overrun, 0 ignored,
0 abort
     15104542 packets output, 17458877900 bytes, 0 underruns
     0 output errors, 0 collisions, 0 interface resets
     0 output buffer failures, 0 output buffers swapped out
     0 carrier transitions
router#


The T1 interfaces show no errors whatsoever, neither do the CSUs.  This
does not appear to impede the flow of data.  This bundle is used as an
access link to a provider's cloud, so I have no access to the other end
of the circuits.  All I know is that they are taking them on an OC48 and
terminating on a Cisco platform.  They claim that they are not seeing
any errors whatsoever.  All my searching indicates this problem is
indicative of a clocking problem.  My clocks are set to external,
provider claims they have a single internal clock source for the entire
OC48.

Any suggestions on how to troubleshoot this further would be
appreciated.  Since I don't see an operational impact (data flows are
unaffected - no drops, no undue latency, etc), might this be a cosmetic
issue?

Thanks,
Michael