On Tue, 13 Feb 2001, Philip Smith wrote:
> At 12:36 13/02/2001 +0530, Vinod Anthony Joseph Cherunni wrote:
>
> >-Traceback= 802B3234 8034E044 8034D830 8034DA70 801FA01C 801A5764 801F4FD8
> >8019B
> >CF4 800272D8 802FA738 802F8318 802CAA1C 802EBC9C 802EBC9C 802CAADC 802CF370
> >Feb 13 11:05:35.262 IST: %SYS-3-INVMEMINT: Invalid memory action (free) at
> >interrupt level
> >The Cisco website states the following -
>
> Don't know. Has anything broken?
I ran into this bug with 12.1(5)T for Cisco RAS units. TAC provided
12.1(5.3)T to correct the problem. This release also corrected the bug
whereby secondary clock source could only be applied to a single
controller.
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