Regarding the same problem,
once the packets come into the PIC I/0 they got split into 64bytes jcells.
The first one is stored in the corresponding fpc. The rest are distributed
via means of a linked list across the other fpc's (shared memory).
One of the guys of the same big iron router vendor was saying that on their
way out they are not sorted and that's why the card cannot reach wire rate.
Well I'm afraid its not the case. Please someone correct me if I'm wrong but
the packet is reassembled by using the same linked list that was created
while it was stored.
Any comments on that?
theo
-----Original Message-----
From: dave bernardi [mailto:dave.bernardi@adelphia.net]
Sent: 21 October 2000 19:11
To: juniper-nsp@puck.nether.net
Subject: Performance problems
Hello,
We are being told by "another" big iron router vendor that Juniper has a
serious flaw with their shared memory architecture primarily with OC-192
PICs but even noticeable at DS-3 rates in certain conditions.
I expect to get more details on the exact problem in a few days.... Has
anyone done independent testing at very high speeds across FPC's. Seems
like a big issue to just slip by everyone.
Thanks,
-- dave bernardi
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