[nsp] 7200 NPE-400 and performance/ problems

[Dennis Peng]

Yep, that is definitely correct.

Dennis

Dmitri Kalintsev [dek at hades.uz] wrote:
> AFAIR, NPE-G1 has 3 PCI buses vs 2 usual (NPE400 et al), and I/O controller
> is occupying the third (it's own) PCI bus instead of hitching the ride on
> the left PA PCI bus. That's why it does not count towards PS bw points. I
> don't have the URL, but it definitely was a Cisco document.
> 
> On Thu, Jul 10, 2003 at 11:57:56AM -0500, Chris Parker wrote:
> > At 06:50 PM 7/10/2003 +0200, Gert Doering wrote:
> > >Hi,
> > >
> > >On Thu, Jul 10, 2003 at 08:06:43AM -0700, Simon Hamilton-Wilkes wrote:
> > >> Better yet, get the Gigabit I/O board and get a fourth Gig port that
> > >> isn't on the backplane.
> > >
> > >Are you sure about that?  All docs I've seen so far seem to suggest that
> > >the IO board ports are counted towards bus 0.
> > >
> > >(It might be different for the C7200-IO-GE/E, but I haven't yet seen
> > >anything stating this, which is why I'm asking)
> > 
> > With the NPE-G1, if you have an I/O controller, the port(s) on that board
> > do not count towards b/w points on the two PA busses.  With
> > 
> > http://www.cisco.com/warp/public/cc/pd/ifaa/prossor/prodlit/npeg1_ds.htm
> > 
> > "Frees the current I/O controller ports from bandwidth limitations, 
> > allowing two PCI buses to be dedicated to the port adapter slots"
> > 
> > Any other NPE/NSE, and the I/O controller does consume b/w points.
> ---end quoted text---
> 
> SY,
> -- 
> D.K.
> _______________________________________________
> cisco-nsp mailing list  cisco-nsp at puck.nether.net
> http://puck.nether.net/mailman/listinfo/cisco-nsp
> archive at http://puck.nether.net/pipermail/cisco-nsp/