[nsp] E3 with both CSUs as clock master?

[Nic McCartney]

I wonder, is there an option on the CSU for loop-timed clocking? (Use
incoming
clock to provide synch for outgoing data?) You could set one as master and
the
other as loop-timed.

Nic


-----Original Message-----
From: cisco-nsp-bounces at puck.nether.net
[mailto:cisco-nsp-bounces at puck.nether.net]On Behalf Of
warner at cats.ucsc.edu
Sent: 30 April 2003 22:11
To: cisco-nsp at puck.nether.net; TBulger at ea.com
Subject: Re: [nsp] E3 with both CSUs as clock master?



>Not specifically Cisco related, but was hoping that someone could
>provide some insight into an unusual problem.  I have an E3 circuit
>which will only stay stable and error free if both CSUs are set as clock
>master..  This goes against everything I have read and seen in the past
>with T3s.  Does anyone have any ideas?  Should I just be happy that it's
>up and not worry about it? :)

In data applications, setting both sides to use their own internal
clock for xmit works OK.  That's because there is no problem if
north and south run at different rates.  What you'll find, however,
is that you can't do an error-free loop test.  When the loopback
relay closes, whatever small difference there is in the frequency
will cause slips to occur.  Creating a situation that is guaranteed
to fail certain tests even when nothing is wrong can be confusing.
In my understanding, that's the biggest problem.

-jim warner,  UCSC


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