[c-nsp] Cisco ISR T3
Kinczli Zoltán
Zoltan.Kinczli at Synergon.hu
Tue Nov 1 17:38:25 EST 2005
hello,
Are you sure? I can remember c72k/PA spec things only, but:
http://www.cisco.com/en/US/partner/products/hw/modules/ps2033/products_tech_note09186a00800d76fb.shtml
Hw 1.0 uses cell mode,
so the PA-A3 forwards *cells* to be reassembled to the NPE/VIP
Hw 2.0 uses frame mode,
the the SAR does reassebly, as you wrote, and the PA-A3 forward *packets*
I do not know the details for the ATM NM, but if some older versions of an
PA-A3 used cell mode, i'd not be too surprised to see that on the NM as well.
>From other hand, in case of the PA-A3 and PA-A6 there is no fallback to public buffers pools, so the CPU has to protect/share the (fixed sized, determined by the type of NPE) private buffer pool between the VCs (ring limits), and i do not know what else...
Anyway, why is performance considerably less with ATM, if everything is the same?
regards,
-zoltan
-----Original Message-----
From: sthaug at nethelp.no [mailto:sthaug at nethelp.no]
Sent: Tue 11/1/2005 8:58 PM
To: Kinczli Zoltán
Cc: cisco-nsp at puck.nether.net
Subject: Re: [c-nsp] Cisco ISR T3
> afaik, there is lot of buffering overhead associated with eth frame <->
> atm cell conversion, and that buffering has to be done by the cpu.
What on earth are you talking about here? Segmentation and reassembly
is done in hardware (by the SAR chip) on any reasonably modern ATM
chipset. The amount of buffering needed for a 1500 byte packet arriving
on an ATM (or E3/T3/OC3) port is the same as the amount of buffering
needed for a 1500 byte packet arriving on an Ethernet port (there are
some differences in encapsulation, of course).
Steinar Haug, Nethelp consulting, sthaug at nethelp.no
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