[c-nsp] full utilization on a T1 causing CRC/frame errors?

[Mark Rogaski]

An entity claiming to be Chris Adams (cmadams at hiwaay.net) wrote:
: 
: A T1 is a synchronous circuit; it is _always_ sending 1.5 megabits per
: second.

To expand a bit on what Chris said.  The source aborts that you are seeing
indicate that the receiver saw a 0x7F bit pattern.  Any patterns like this
in he user data is handled by bit stuffing.  If you are seeing aborts and
CRC errors, the circuit is encountering bit errors.

This has nothing to do with utilization.  Utilization problems will result
in FECN/BECN or dropped output drops.  I can't say I've seen input errors
due to output conditions, but I have seen equipment that didn't use
separate queueing for LMI which resulted in LMI failures under load.

The ILEC is feeding you a line of horse puckey.

Mark 

-- 
[]                    |   A scientist can discover a new star, but he
[] Mark Rogaski       |   cannot make one. He would have to ask an engineer
[] wendigo at pobox.com  |   to do that.
[] mrogaski at cpan.org  |   -- Gordon L. Glegg, American Engineer, 1969
[]                    |
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