[c-nsp] Timing slips on an 2811

[james edwards]

I am getting timing slips on a ATM T-1 when the clocking is set to line.
Setting it to internal is of course no better.
I am using a VWIC2-1MFT-T1/E1 on IOS c2800nm-spservicesk9-mz.124-21a.bin.
Links to troubleshooting docs
about slips or suggestions on what is wrong with the config will be
appreciated.


#sho controllers t1 0/0/0
T1 0/0/0 is up.
  Applique type is Channelized T1
  Cablelength is short 330
  No alarms detected.
  alarm-trigger is not set
  Soaking time: 3, Clearance time: 10
  AIS State:Clear  LOS State:Clear  LOF State:Clear
  Version info Firmware: 20071011, FPGA: 13, spm_count = 0
  Framing is ESF, Line Code is B8ZS, Clock Source is Line. <----------------
  CRC Threshold is 320. Reported from firmware  is 320.
//////
Total Data (last 12 15 minute intervals):
     0 Line Code Violations, 0 Path Code Violations,
     1512 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
     1512 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail
Secs


Here is the config:

card type t1 0 0

network-clock-participate wic 0
network-clock-participate aim 0

controller T1 0/0/0
 mode atm aim 0
 framing esf
 linecode b8zs
 cablelength short 330
clock source line

interface ATM0/0/0
 description Circuit ID xxxxxx
 no ip address
 no scrambling-payload
 no atm ilmi-keepalive
!
interface ATM0/0/0.1 point-to-point
 description ATM T-1 to xxx
 ip address x.x.x.x x.x.x.x
 ip access-group 100 out
 snmp trap link-status
 pvc 1/32
  cbr 1536
  encapsulation aal5snap


-- 
James H. Edwards
Senior Network Systems Administrator
Judicial Information Division
jedwards at nmcourts.gov