[c-nsp] Cisco Switch Packet Buffering Matrix?

[Jeff Bacon]

> > The 2960/3560 make no mention of packet buffer arrangement or depth.
> >
> > But I'm somewhat surprised that the 2950 has as much as 4x the depth
of
> > the 3550 in terms of packet buffering(!).
> 
> Don't be. The newer switches have even less...
> 
> *2960G - only 384 kB per ASIC - i.e. 8 GE (!) ports.

I don't know where I found/got this, but IIRC 3560/3750[G] is 2MB
receive buffer per port-asic, with either 4 or 8 ports per port-asic
depending on if it's a 24 or 48-port switch. Or is that shared tx/rx?
No, I think the tx is something fairly trivial. 

It's all ok, even with bursty traffic (sorta), as long as your inputs
match your outputs, e.g. there's nothing to buffer. It's when that's not
the case that everything goes to hell.

The E/X models are completely different, no idea on those. (Have a
couple of -Es coming. Only reason I accept them for the purpose is that
I'm going to use them to break up a 10G inter-datacenter-link into 10 1G
channels, so there's no reason for anything to have to buffer...)