[c-nsp] E1 packet loss

[Aaron]

+1
clock line
crc4

On Fri, Jun 11, 2010 at 08:41, Martin Moens <Moens at carrier2carrier.com>wrote:

> E1 errors are often caused by clocking issues - are you shure you should
> provide clocking on the A-end?
> Often clocking is provided by the network.
> Tried to switch on crc4?
>
> Martin
>
>
> On Friday, 11 June, 2010 14:18 Rens <> wrote:
>
> > Hi all,
> >
> > I have 2 routers that are connected via a 3rd party E1 circuit.
> > When I ping between my routers I have packet loss.
> > I have done a BER test on the E1 circuit which comes out clean.
> > Already replaced both E1 cards and my cabling, but still having
> > packet loss (between 30 & 10% depending on size)
> >
> > I have followed the E1 error events troubleshooting for the line code
> > violations & path code violations but line code is configured
> > correctly...
> >
> > What are the next steps that I can take?
> > Below is my config + the show controller output
> >
> > Side A:
> >
> > controller E1 0/1
> >  framing NO-CRC4
> >  clock source internal
> >  channel-group 0 timeslots 1-31
> >
> > interface Serial0/1:0
> > ip address x.x.x.1 255.255.255.252
> >
> > show controllers E1 0/1
> > E1 0/1 is up.
> >   Applique type is Channelized E1 - balanced
> >   No alarms detected.
> >   alarm-trigger is not set
> >   Version info Firmware: 20040108, FPGA: 11
> >   Framing is NO-CRC4, Line Code is HDB3, Clock Source is Internal.
> >   CRC Threshold is 320. Reported from firmware  is 0.
> >   Data in current interval (24 seconds elapsed):
> >      0 Line Code Violations, 0 Path Code Violations
> >      0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
> >      0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0
> > Unavail Secs
> >
> > Side B:
> >
> > controller E1 0
> >  framing NO-CRC4
> >  channel-group 0 timeslots 1-31
> >
> > interface Serial0:0
> > ip address x.x.x.2 255.255.255.252
> >
> > sh controllers E1 0
> > E1 0 is up.
> >   Applique type is Channelized E1 - balanced
> >   No alarms detected.
> >   alarm-trigger is not set
> >   Version info Firmware: 20040928, FPGA: 11, spm_count = 0
> >   Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
> >   CRC Threshold is 320. Reported from firmware  is 320.
> >   Data in current interval (20 seconds elapsed):
> >      2689 Line Code Violations, 53 Path Code Violations
> >      0 Slip Secs, 0 Fr Loss Secs, 20 Line Err Secs, 0 Degraded Mins
> >      0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 20
> > Unavail Secs
> >
> > Regards,
> >
> > Rens
> >
> >
> > _______________________________________________
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>
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