[c-nsp] E1 packet loss

[Rens]

Yes they provide clocking but I have already tried setting both to line but
I have the same problem, but the BER test should also give problems when
clocking is wrong no?

-----Original Message-----
From: Mackinnon, Ian [mailto:Ian.Mackinnon at atosorigin.com] 
Sent: vendredi 11 juin 2010 14:38
To: Rens; cisco-nsp at puck.nether.net
Subject: RE: [c-nsp] E1 packet loss

Is your provider providing clock?
You are set for clock source internal, try setting it to line.

Note my recent experience of traditional TDM type circuits is that there is
nobody left at the providers with any clue about TDM.



> -----Original Message-----
> From: cisco-nsp-bounces at puck.nether.net [mailto:cisco-nsp-
> bounces at puck.nether.net] On Behalf Of Rens
> Sent: 11 June 2010 13:18
> To: cisco-nsp at puck.nether.net
> Subject: [c-nsp] E1 packet loss
> 
> Hi all,
> 
> I have 2 routers that are connected via a 3rd party E1 circuit.
> When I ping between my routers I have packet loss.
> I have done a BER test on the E1 circuit which comes out clean.
> Already replaced both E1 cards and my cabling, but still having packet
> loss
> (between 30 & 10% depending on size)
> 
> I have followed the E1 error events troubleshooting for the line code
> violations & path code violations but line code is configured
> correctly...
> 
> What are the next steps that I can take?
> Below is my config + the show controller output
> 
> Side A:
> 
> controller E1 0/1
>  framing NO-CRC4
>  clock source internal
>  channel-group 0 timeslots 1-31
> 
> interface Serial0/1:0
> ip address x.x.x.1 255.255.255.252
> 
> show controllers E1 0/1
> E1 0/1 is up.
>   Applique type is Channelized E1 - balanced
>   No alarms detected.
>   alarm-trigger is not set
>   Version info Firmware: 20040108, FPGA: 11
>   Framing is NO-CRC4, Line Code is HDB3, Clock Source is Internal.
>   CRC Threshold is 320. Reported from firmware  is 0.
>   Data in current interval (24 seconds elapsed):
>      0 Line Code Violations, 0 Path Code Violations
>      0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
>      0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail
> Secs
> 
> Side B:
> 
> controller E1 0
>  framing NO-CRC4
>  channel-group 0 timeslots 1-31
> 
> interface Serial0:0
> ip address x.x.x.2 255.255.255.252
> 
> sh controllers E1 0
> E1 0 is up.
>   Applique type is Channelized E1 - balanced
>   No alarms detected.
>   alarm-trigger is not set
>   Version info Firmware: 20040928, FPGA: 11, spm_count = 0
>   Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
>   CRC Threshold is 320. Reported from firmware  is 320.
>   Data in current interval (20 seconds elapsed):
>      2689 Line Code Violations, 53 Path Code Violations
>      0 Slip Secs, 0 Fr Loss Secs, 20 Line Err Secs, 0 Degraded Mins
>      0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 20 Unavail
> Secs
> 
> Regards,
> 
> Rens
> 
> 
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