[c-nsp] Cisco's new 4500-X 10G Aggregation Switches

[Alan Buxey]

Hi,

> What type of mtrie stride could possibly do this? IPv4 8-8-8-8 and IPV6
> 16-16-16-16-16-16-16-16, this would make IPv6 mtrie depth and width 2x of
> IPV4.
> For them to be same depth IPv6 stride would need to be
> 4294967296-4294967296-4294967296-4294967296 if you could have that wide
> stride, IPv4 could be looked up from flat mtrie.

hmmm, generically, there shouldnt be such an issue for handling traffic - as
the IPv6 packet is likely to be same size or smaller (smaller header) as IPv4..
which then would suggest that the issue is in stages such as address handling and
lookups.  now 64bit CPU isnt the best for 128bit addresses - so theres going to
be some hit there - what you need is some GPU technology for doing address mashing
rather than the old CPU way... so thats ASIC territory.  

it is a shame that we are trying to move from IPv4 to IPv6....but even the latest
hardware from Cisco gives us a big performance hit for doing that - this 2x slowdown 
is nothing new...its been around on all their devices :-|

> It's very difficult for me to understand how to do these in same constant
> time, without having very poor IPV4 implementation.

2 data paths?  IPv4 go one way, IPv6 go another... but then you have to duplicate ALL
the stuff onboard - expensive! noone wants to pay more for IPv6 (just like noone wanted to
pay more for IPv4 when they were migrating from DECNET/ATALK/IPX)

alan