[c-nsp] ASR-100x intro

[Mack McBride]

The TCAM on the ASR1k is not used for FIB. That is for QOS and ACL handling.
Those figures are in bits and it generally takes 144 or 288 bits to store an entry (more bits for port information).
The 144/288 division is used by ACL TCAM in the 6509.  My understanding is that the ASR uses a slightly different
division if port information is required but I haven't seen documentation.
The TCAM I am intimately familiar with from a general chip perspective but not how the ASR does it specifically.

My understanding is that the MB from the QFP in the document you referenced are used for the FIB but anything
that doesn't fit can be offloaded to slower DRAM (still looking for confirmation).  I haven't gotten a good explanation 
from anyone as to what happens when the QFP memory is exhausted.

LR Mack McBride
Network Architect

-----Original Message-----
From: Nick Hilliard [mailto:nick at foobar.org] 
Sent: Friday, February 08, 2013 11:59 AM
To: Mack McBride
Cc: Adam Vitkovsky; cisco-nsp at puck.nether.net
Subject: Re: [c-nsp] ASR-100x intro

On 08/02/2013 17:27, Mack McBride wrote:
> It seems they could get handled in software but the ESP is basically 
> software anyway.

packet destination lookup is handled in TCAM on the asr1k.  The amount of TCAM is listed on page 11 of:

> http://www.cisco.com/en/US/prod/collateral/routers/ps9343/data_sheet_c
> 78-450070.pdf

The TCAM size is measured in megs rather than prefixes, as this is a more natural way of handling it.  You're right that it's opaque though - the figures for ipv4 are the same as for ipv6 for the ESP40/ESP40/ESP100, and only 2x for the ESP20.  It would be very interesting if Cisco could provide some details on how TCAM carving is handled on these boxes.


Nick

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Archive ref: "Cisco ASR 1000 Series Embedded Services Processors" data sheet, docid: C78-450070-26