[c-nsp] RAM thing

Saku Ytti saku at ytti.fi
Tue Feb 18 08:24:24 EST 2014

On (2014-02-18 12:44 +0100), Lukas Tribus wrote:

> No, I don't know. That was rather a humble assumption (if the control plane RAM
> is ECC, shouldn't the forwarding plane also be ECC?).

There are lot of memories for different places where packet may live during
it's trip inside the HW.

it's very possible to have something like this:
wire => ring => sram => dram => sram => ring => wire
        1st     2nd     3rd     4th     5th

ring in phy
sram acting as cache, as we need one (partial) copy towards lookup and one
copy towards long term slow storage at dram.
with any luck ingress+egress cards are sharing the dram storage so that is not
copied around

And I probably don't understand it well enough, there may be even more places
where it may live during traversing inside router.

L2 is relatively safe, since FCS/CRC is strong and you don't recalculate it,
so if your switch mangles your frame, you'll know about it.
L3 is problematic, if your router mangles your frame, you probably won't know
about, unless you're lucky and it happens in IPv4 header, even this case in
MPLS networks it's very hard to track down, as you won't see it where it
happened, you'll see it in every egress PE.

As this happens in real networks (look at your counters) I think it's pretty
safe to assume it's fairly typical that devices have some memories which do
not offer error correction/checking.


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