[c-nsp] ISR 4451-X route table size

Phil Mayers p.mayers at imperial.ac.uk
Thu Jan 15 08:20:49 EST 2015

On 15/01/15 12:26, sthaug at nethelp.no wrote:
>>> Interesting your distinction because Cisco says that the 4451:
>>> "The product???s innovative hardware design splits the control and data planes between two multi-core CPUs???
>> Indeed, that's where my definition would not trivially apply either way :-)
>> (And given how fast multipurpose CPUs have become, we see this in other
>> areas as well - like "SSL offloading PCI boards" that you could add to
>> a web server for decent HTTPS performance... most of that has just plain
>> disappeared with modern CPUs...)
> For me the relevant question is often: Can the box handle line rate,
> or close to it, with minimum sized packets (and any access lists,
> services, QoS etc that you need)? If it can, great - otherwise you're
> opening yourself to a DoS attack at some point.

I tend to agree. I like predictable performance that degrades sensibly, 
not suddenly crossing a threshold and failing to work at all. Whether 
it's FPGA, TCAM or CPU and fast RAM is in theory irrelevant.

In practice, vendors tend to be rosy about their performance, and the 
underlying architecture can indicate the likely performance window ;o)

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