[c-nsp] netflow restrictions on ASR920

[James Bensley]

On 12 January 2017 at 03:14, Nick Cutting <ncutting at edgetg.com> wrote:

> *         FPGA monitor only 1Gbps traffic rate (with minimum frame size of 100 byte). The accounting is accurate only when the overall traffic monitored is within 1Gbps.
...

> So If I am reading this correctly - my 10gig link will not have correct information when the traffic goes over 1 gig in untilization?
> Is this due to the ASIC FPGA logic on this hardware?
>
> I cannot use PBR on this interface
> And I cannot enable BFD?

I'm not entirely sure as I haven't tried NetFlow on the ASR920's (it
looks like a disaster so we haven't placed them anywhere we would need
NetFlow) but is that limit perhaps relating to CPU punted traffic
only?

My understanding is as follows: All PHY controllers connect to the
Cylon ASIC so it should be a compact forwarding path, traffic comes in
one port (be it 1G or 10G etc.), local forwarding logic and TCAM
on-chip (Cylon) looks up correct egress port and re-write details,
Cylon sends the traffic to the appropriate egress PHY.

There is a PCIe link between the Cylon ASIC and CPU, and there is a
PCIe link from the Cylon to the FPGA and then from the FPGA to the
CPU. Given the direct link from Cylon to CPU I’m not sure why the FPGA
would limit NetFlow for “normal” (non-punted) traffic, I would assume
the CPU would handle this. I’m not fully aware of how the
design/topology is working here. There is a cylon_mgr process which I
presume runs on the CPU (it sites outside of IOSd). I’m not sure what
functions the FPGA is handling that the Cylon can’t handle itself.
There is 2GB DDR3 memory hanging off the FPGA and 2GB DDR3 memory
handing off the CPU and I *think* the FPGA attached memory is running
at a faster clock. There is 12MB of on-chip packet buffers on the
Cylon, so why are there two lots of DDR3 memory? Again not sure what
is being offloaded to the CPU and what is being off loaded to the
FPGA. Maybe NetFlow is off loaded to the FPGA?

If anyone can elaborate I’d like to know of if anyone from Cisco wants
to chime in please do. It’s very annoying they aren’t clearer about
these things as anything we want to do we have to lab test it and work
it out for our self (typical questions like “how many ‘features’ or
which ‘features’ can I enable and still get line rate or X Mbps/Gbps,
because we aren’t told how the features are working).


Cheers,
James.