[j-nsp] juniper trinity

[Richard A Steenbergen]

On Fri, Oct 30, 2009 at 05:35:45PM -0700, Judah Scott wrote:
> The datasheet for the new MX 3D line cards is a little strange.  Assuming
> that a find-and-replace of "KB" to "K" will make it more coherent, this is
> an awesome amount of queues when comparing to competitors.  However, the new
> FPC/PIC-like card strategy is in 30Gb/s and 60Gb/s flavors.  Given that the
> 16x10GE card is oversubscribed this looks like the old DPC 4x10Gb/s stacked
> complex design (except now it is 4x30Gb/s?).  I guess this because the
> numbering is much like the DPC in that they are 0/0-3 1/0-3 2/0-3 3/0-3.
> Would Juniper really come out with a 30Gb/s (full duplex) chipset?  With no
> 40GE announcement I can only assume this chipset is going to be damn hard
> (or expensive) to do 40GE interfaces.

My understanding is that Trinity is more of an architecture than a
single chip, so while the initial MX release will be 30Gbps per PFE the
architecture itself is intended to support 40GE and 100GE in the future.

The story I've heard is the 16x10GE card will be powered by (4) 30Gbps
PFEs, with each group of 4 ports landing on a PFE. Each existing SCBs
will be able to provide 10Gbps of fabric capacity to each PFE, and on
MX960 you'll be able to run all 3 SCBs in parallel (instead of the
current configuration of 2 active plus 1 in standby) to get your 30Gbps
of fabric capacity per group of 4 ports. I'm not sure if there will be
any benefits to local switching on the same PFE or not, but even if 
there are it seems like this will just help fabric redundancy not 
provide > 30Gbps of forwarding capacity.

Of course the biggest problem with the 16x10GE card is that it is SFP+
and can't do WAN PHY, so it will only be useful for simple datacenter
SR/LR configurations and not in any carrier roles.

-- 
Richard A Steenbergen <ras at e-gerbil.net>       http://www.e-gerbil.net/ras
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