[j-nsp] MX80 max MAC addresses

Richard A Steenbergen ras at e-gerbil.net
Thu Nov 4 10:19:02 EDT 2010

On Thu, Nov 04, 2010 at 12:31:07PM +0100, Hendrik Kahmann wrote:
> Hi Sven,
> I just contacted an insider :-)
> The MX80 can be interpreted as a single DPC with an on-top 
> Routing-Engine and some chassis-stuff around it so the limit of 1 
> Million MAC-Addresses applies for it.

The MX80 is a single MPC using the new Trio ASICs, which means that it 
has roughly double the capacity of the original DPCs. You can see this 

TAZ-TBB-0(mx80-1.lab1 vty)# sh luchip 0    
   JTAG_ID:  0x1142957f, Version 1.1
    RLDRAM:  576 Mb by 4 devices at 533 MHz.
      DDR3:  1024 Mb by 2 devices at 733MHz/CL10.
      TCAM:  Installed.

576Mbit / 8 = 72MB - ECC parity = 64MB RLDRAM modules * 4 per pfe, which 
is double size of classic DPCs. This is good enough for 2mil+ routes, 

Unlike other platforms, the MX architecture if very flexible in how it 
uses its memory. For example, when a Cisco SUP720-3BXl says "1 million 
IPv4 routes", this means precisely 1 million, because they have exactly 
72MB of TCAM and each IPv4 route takes a 72-bit entry, so they can fit 
exactly 2^20 entries (assuming no other IPv6/MPLS/multicast routes). On 
the MX the limits are much more arbitrary, as long as it all fits into 
the (very very large) lookup memory.

Most of the limits you do see are either completely marketing based 
(i.e. they had to pick a nice round number to put on a datasheet), or 
the result of internal implementation details. Foe example, until 10.4 
the firewall filter index was a 16 bit value, so you could only have a 
max of 64k filters on a box. They had customer demand for higher, so in 
10.4 they bumped it to a 22 bit index on MX, and you can now have over 4 
million filters. A lot of the current limits are set that way not 
because they're all that can be done on the modern hardware, but because 
they're all that was supported 8 years ago on the original T-series 
chips, and nobody has yet had a need for bigger. If you look at the sw 
releases over the last few years, you'll see that they've been routinely 
increasing the scaling numbers to take advantage of new platforms, 
particularly for the MX, which uses the newest and most capable 
hardware. Of course this is also partially responsible for the bloat, 
where newer code no longer runs on older hardware, but at least with 
MX80/Trio you're looking at the latest generation and the most advanced 
thing Juniper makes, so you should be safe for a long long time. :)

Now that said, from everything I can read it looks like the scaling 
design for MAC addresses was 256k for DPCs and 512k for MPCs. I have 
absolutely no idea if there is a fixed limit behind that, or if it's an 
arbitrary number. On DPCs it may have been related to what the EZchip 
could do, so on Trio the limitations may be totally different. It's 
entirely possible that they just haven't written the software to take 
advantage of the increased capacity yet, you'd have to ask Juniper.

Richard A Steenbergen <ras at e-gerbil.net>       http://www.e-gerbil.net/ras
GPG Key ID: 0xF8B12CBC (7535 7F59 8204 ED1F CC1C 53AF 4C41 5ECA F8B1 2CBC)

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