[j-nsp] M20 SSB slot 0 failures

[Chris Cappuccio]

Hi,

I have four M20 chassis with continuous slot 0 SSB failures. 

These are from two completely different vendors..

I would think, oh, a bad chassis, but I am getting this same result with a variety of chassis and SSB cards.  I do have chassis that don't display this failure, with the same SSB cards.  This is what leads me to believe that I am hitting a rash of bad crap.

The failure is as follows.  Any SSB tests out fine in slot 1.  But in slot 0, the same SSBs fail.  Slot 0 often "Fails over" to slot 1 in operation if both SSBs are populated in these chassis.

Is this some kind of known problem?  Or am I just the most unlucky person in the Juniper M20 world?

Success in slot 1
-----------------

SSB1( vty)# bringup chassis slot-state 1 diag
Slot 1 state changed from 'on-line' to 'diagnostics'

SSB1( vty)# diagnostic set mode manufacturing

SSB1( vty)# diag clear log

SSB1( vty)# diag bchip 1 sdram
[Waiting for completion, a:abort, p:pause]
B SDRAM (Slot 1) test
phase 1, pass 1, B SDRAM (Slot 1) test: Address Test
phase 2, pass 1, B SDRAM (Slot 1) test: Pattern Test
phase 3, pass 1, B SDRAM (Slot 1) test: Walking 0 Test
phase 4, pass 1, B SDRAM (Slot 1) test: Walking 1 Test
phase 5, pass 1, B SDRAM (Slot 1) test: Mem Clear Test
B SDRAM (Slot 1) test completed, 1 pass,  0 errors


SSB1( vty)# diag bchip 1 sdram
[Waiting for completion, a:abort, p:pause]
B SDRAM (Slot 1) test
phase 1, pass 1, B SDRAM (Slot 1) test: Address Test
phase 2, pass 1, B SDRAM (Slot 1) test: Pattern Test
phase 3, pass 1, B SDRAM (Slot 1) test: Walking 0 Test
phase 4, pass 1, B SDRAM (Slot 1) test: Walking 1 Test
phase 5, pass 1, B SDRAM (Slot 1) test: Mem Clear Test
B SDRAM (Slot 1) test completed, 1 pass,  0 errors


Fail in slot 0
--------------

SSB0( vty)# bringup chassis slot-state 0 diag
Slot 0 state changed from 'diagnostics' to 'diagnostics'

SSB0( vty)# diagnostic set mode manufacturing

SSB0( vty)# diag clear log

SSB0( vty)# diag bchip 0 sdram 
[Waiting for completion, a:abort, p:pause]
B SDRAM (Slot 0) test
phase 1, pass 1, B SDRAM (Slot 0) test: Address Test

*** Fatal error during B SDRAM (Slot 0) test, pass 1,
Data did not compare, Slot 0 (NIC0 B chip SDRAM banks ref. des. U?)


B SDRAM (Slot 0) test completed, 1 pass,  1 error

[Jan  5 21:34:17.356 LOG: Err] Data Error: Bank 0 (global cell 0x3e52): Expected 0x5280001f, Observed 0x200200