[j-nsp] FPC CPU

[Saku Ytti]

On (2012-09-24 14:41 +0400), Nick Kritsky wrote:

> For M, MX, EX series there is an OID for monitoring FPC CPU.
> Question - what is this CPU for? What are we measuring here?

It's abstraction model popularized by GSR. Route engine does not need to
know anything about how to program hardware. Route engine talks to general
purpose CPU on the linecard and this linecard handles updating the actual
hardware.
Also linecard does not talk to RP, so if linecard needs to give some packet
software handling (say BGP, TTL exceeded...) it won't give it to RP, it'll
give it to LC CPU, which then may or may not give it to RP.
In most cases these are freescale powerPC cpus, historically powerquicIII
but in latest generation hardware QorIQ processors.

> Is it raw throughput stats of an ASIC, or CPU time that is used for
> some FPC-level tasks by some utility processor (BFD? LACP? STP?
> J-Flow?).

Yeah these can be in NPU (Trio does some of this) LC CPU or RE. Depends.
But what is crucial is that when you need to talk to linecard, you do it
via LC CPU, not directly from RP.

> What happens when this value reaches 100% (card freeze, drops, LACP link loss)?
> Appreciate your help.

It's hard to answer, there are more than one punt queue towards the LC CPU,
some packets get priority treatment some don't. If you know exactly how
this work, then it might be DoS vector (if you knew what to do, you could
bring GSR down with sub 300kpps (think 200Mbps))

-- 
  ++ytti