[j-nsp] FPC/PFE route scaling

[Rutger Bevaart]

Hello list,

I'm having a hard time understanding route scaling on the bigger M and MX boxes. In a CFEB based box maximum FIB is around 500k due to the limited SRAM on the CFEB holding the FIB. On a CFEB-E this is increased.

Now looking at the M320 or MX240 the FIB is present on all FPC boards in each PFE, correct? What is the architectural difference when using a distributed setup, and how does it affect maximum FIB size? Eg. On an FPC3-E2 in an M320 what can be expected to be the limit?

Regards,
Rutger