[j-nsp] CoS buffer size

[Dan Peachey]

>
> Hey Dan,
>
>
> > I must be missing something, but it seems that regardless of what I set
> as
> > a temporal buffer, the byte buffer value assigned doesn't appear to
> change.
>
> Can you give
>
> CLI config (TCP, shaper and queues)
> show cos halp ifl X
> show qx N tail-rule Y 0 0
> show qx N q Z queue-length
>
> With two different temporal values in queues.
>
> Remember that you must configure guaranteed-rate for shaping to work in QX
> as
> accustomed to DPCE and MQ. Otherwise all your queues are in excess region.
>
>
Hi Saku,

Requested outputs below (this is not a finished policy, for now I'm just
playing with buffers mainly).

IFD is in PIR mode as only PIR is configured (interface could be
oversubscribed so configuring guaranteed rate doesn't make sense). As I
understand it, queues are therefore always in excess (apart from
rate-limited queue) with weight proportional to the transmit-rate (correct
me if I am wrong).

Thanks,

Dan

--

class-of-service {
    traffic-control-profiles {
        10M {
            scheduler-map 10M_COS;
            shaping-rate 10m;
        }
    }
    interfaces {
        xe-0/0/1 {
            unit 2000 {
                output-traffic-control-profile 10M;
            }
        }
    }
    scheduler-maps {
        10M_COS {
            forwarding-class Q5 scheduler RT;
            forwarding-class Q2 scheduler SIG;
            forwarding-class Q1 scheduler PRI;
            forwarding-class Q3 scheduler NC;
            forwarding-class Q0 scheduler BE;
        }
    }
    schedulers {
        NC {
            transmit-rate percent 1;
            buffer-size temporal 500k;
            priority medium-high;
            excess-priority high;
        }
        RT {
            transmit-rate {
                percent 24;
                rate-limit;
            }
            buffer-size temporal 20k;
            priority high;
        }
        SIG {
            transmit-rate percent 2;
            buffer-size temporal 500k;
        }
        PRI {
            transmit-rate percent 24;
            buffer-size temporal 165k;
        }
        BE {
            transmit-rate percent 24;
            buffer-size temporal 165k;
        }
    }
}


NPC0(pe1-RE0 vty)# show cos halp ifl 329
IFL type: Basic

--------------------------------------------------------------------------------
IFL name: (xe-0/0/1.2000, xe-0/0/1)   (Index 329, IFD Index 164)
    QX chip id: 0
    QX chip dummy L2 index: 4
    QX chip Scheduler: 4
    QX chip L3 index: 4
    QX chip base Q index: 32
    Number of queues: 8
Queue    State        Max       Guaranteed   Burst  Weight Priorities
Drop-Rules
Index                 rate         rate      size            G    E   Wred
 Tail
------ ----------- ----------- ------------ ------- ------ ----------
----------
    32  Configured    10000000            0  131072    320   GL   EL    4
  0
    33  Configured    10000000            0  131072    320   GL   EL    4
  0
    34  Configured    10000000            0  131072     26   GL   EL    4
  0
    35  Configured    10000000            0  131072     13   GM   EH    4
127
    36  Configured    10000000            0  131072      1   GL   EL    0
255
    37  Configured    10000000      2400000  131072    320   GH   EH    4
193
    38  Configured    10000000            0  131072      1   GL   EL    0
255
    39  Configured    10000000            0  131072      1   GL   EL    0
255

Rate limit info:
    Q 5: Bandwidth = 2400000, Burst size = 73536. Policer NH:
0x3077afaa0003b000

    Index NH: 0xda4be18980801006


NPC0(pe1-RE0 vty)# show qxchip 0 tail-rule 33 0 0
Tail drop rule configuration   : 33
        ref_count    : 0
     Drop Engine 0   :
       Tail drop rule ram address   : 00000840
                       threshold    : 2686976 bytes
                            shift   : 14
                         mantissa   : 164
     Drop Engine 1   :
       Tail drop rule ram address   : 00000840
                       threshold    : 2686976 bytes
                            shift   : 14
                         mantissa   : 164


NPC0(pe1-RE0 vty)# show qxchip 0 tail-rule 34 0 0
Tail drop rule configuration   : 34
        ref_count    : 0
     Drop Engine 0   :
       Tail drop rule ram address   : 00000880
                       threshold    : 2801664 bytes
                            shift   : 14
                         mantissa   : 171
     Drop Engine 1   :
       Tail drop rule ram address   : 00000880
                       threshold    : 2801664 bytes
                            shift   : 14
                         mantissa   : 171


NPC0(pe1-RE0 vty)# show qxchip 0 q 32 queue-length
QX Queue Index: 32
   Current instantaneous queue depth : 0 bytes

   WRED TAQL queue depth             : 0 bytes

   Configured queue depth:
         region   color   queue-depth
         ------   -----   -----------
           0       0         4096
           0       1         4096
           0       2         4096
           0       3         4096
           1       0         3264
           1       1         3264
           1       2         3264
           1       3         3264
           2       0         512
           2       1         512
           2       2         512
           2       3         512
           3       0         0
           3       1         0
           3       2         0
           3       3         0