[j-nsp] MX960 with 3 RE's?

[Adam Vitkovsky]

> From: Saku Ytti [mailto:saku at ytti.fi]
> Sent: Friday, January 15, 2016 12:45 AM
>
> On 15 January 2016 at 01:39, Christopher E. Brown
> <chris.brown at acsalaska.net> wrote:
> > The 30Gbit nominal (actual 31.7 or greater) limit per trio applies to
> > the MPC1 and 2 cards but the quad trio interconnect in the 16XGE is
> > wired up diff with additional helpers and can do the full 40G per bank.
>
> There is actually one difference in MPC1/MPC2 and 16XGE. MPC1/MPC2 do
> binary multicast replication, while 16XGE does unary.
I didn't know there's even worse performance than the binary multicast replication (glad they did not do the head-end replication)

>
> So if your box is full of 16X10GE, multicast stream hops from NPU to NPU, so
> every NPU gets the stream replicated at different time (i know stock
> exchanges running MX and masturbating over nanoseconds in switching
> latency, while they are doing three orders of magnitude larger jitters in MX
> replication).
> While if box is full of MPC1/MPC2, each card or NPU, will send copy to two
> other NPU, for dramatically more efficient replication. (Of course the
> theoretically correct way is to replicate in fabric, but I'm not paying one cent
> for the right solution for this feature which should be just checkbox item at
> best)
>
Well certainly not if you're doing IPTV on a fully loaded box where you just overload the Fabric or stock exchange where you are obligated to deliver the info to everyone at the same time or HFT where nanoseconds actually do matter.

> This also means that if you run multicast, trio needs 80Gbps of fabric capacity
> for those 40Gbps of WAN capacity. DPCE/ichip has this, DPCE is 40Gbps, but
> has 80Gbps of fabric capacity.
> SCBE and MPC2 has this, 80Gbps of WAN capacity and 160Gbps of fabric
> capacity.
> While 16XGE needs just same fabric capacity as WAN capacity.
>
What to say, there's a reason why Juniper is cheaper. One has to know if it fits his/her implementation (which is hard btw with the sparse documentation at hand).


adam


        Adam Vitkovsky
        IP Engineer

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