[j-nsp] what’s the story behind MPC5E

david.roy at orange.com david.roy at orange.com
Fri May 20 11:08:45 EDT 2016


This is the same design for MPC6e PFE and I didn't see any issue with this design. I also didn't see any specific issue due to this design in POC where we stressed the PFE. XL ressources are just shared. For Inter XM forwarding, the shared XL is not used but the fabric links is used. 


-----Message d'origine-----
De : Adam Vitkovsky [mailto:Adam.Vitkovsky at gamma.co.uk] 
Envoyé : vendredi 20 mai 2016 17:00
À : ROY David DTSI/DERS; juniper-nsp at puck.nether.net
Objet : RE: what’s the story behind MPC5E

> Of david.roy at orange.com
> Sent: Friday, May 20, 2016 3:24 PM
>
> MPC5e has one PFE (260Gpbs) made of 2 XM chip, 1 XL and 1 XQ (only for 
> Q
> mode)
>
OMG, now that's bummer like it has two PFEs but they share a common XL :) Now that's got to be the stupidest TRIO design I've seen so far.
I'd love to see how arbitration as well as backpressure is done in this case since now two independent arbiters(since arbiter is in XM) are going to fight over XL resources.


adam









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