[j-nsp] MPC5EQ Feedback?

[Scott Harvanek]

Adam,

I thought that the MPC3E and MPC5E had the same generation Trio w/ XL and XQ chips?  Just the MPC5E has two XM chips.  

Scott H



> On Nov 1, 2017, at 10:28 AM, <adamv0025 at netconsultings.com> <adamv0025 at netconsultings.com> wrote:
> 
>> Scott Harvanek
>> Sent: Tuesday, October 31, 2017 6:57 PM
>> 
>> Hey folks,
>> 
>> We have some MX480s we need to add queuing capable 10G/40G ports to
>> and it looks like MPC5EQ-40G10G is going to be our most cost effective
>> solution.  Has anyone run into any limitations with these MPCs that aren’t
>> clearly documented?
>> 
>> We intend to use them for L3/VLAN traffic w/ CoS/Shaping.  Currently we’re
>> doing that on MPC2E NG Qs w/ 10XGE-SFPP MICs , any reason we couldn’t
>> do the same on this along with the adding of the 40G ports? Any Layer3
>> limitations or the normal 2MM/6MM FIB/RIB?
>> 
> Hey Scott,
> I'd rather go with a standard Trio architecture i.e. one lookup block one buffering block (and one queuing block) -so mpc3 or mpc7. 
> To me it seems like 4 and 5 are just experiments with the Trio architecture that did not stood the test of time. 
> 
> adam
> 
>