[j-nsp] MPC5EQ Feedback?

[Scott Harvanek]

Pavel,

Thank you for the detailed comments, this is basically what I understood to be the case.  I’m running MPC3 NG EQs right now which as you note is the same as the MPC5, we haven’t had any issues so it sounds like the MPC5E should achieve what we need and operate as we expect.

Scott H



> On Nov 1, 2017, at 11:07 AM, Pavel Lunin <plunin at gmail.com> wrote:
> 
> 
> 
> There were two versions of MPC3:
> 
> 1. MPC3 non-NG, which has a single XM buffer manager and four LU chips (the old good ~65 Mpps LUs as in "classic" MPC1/2/16XGE old trio PFEs).
> 2. MPC3-NG which is based on exactly the same chipset as MPC5, based on XM+XL.
> 
> MPC4 is much like MPC3 non-NG though it has two LUs instead of four with a new more "performant" microcode.
> 
> XL chip (extended LU), which is present in MPC5/6 and 2-NG/3-NG has also multiple ALU cores (four, IIRC) but in contrast to MPC3 non-NG and MPC4 these cores have a shared memory, so they don't suffer from some limitations (like not very precise policers) which you can face with multi-LU PFE architectures.
> 
> MPC7 has a completely new single core 400G chip (also present in the recently announced MX204 and MX10003).
> 
> This said, I find MPC4 quite not bad in most scenarios. Never had any issues, specific to its architecture.
> 
> P. S. Finally this choice is all about money/performance.
> 
> 
> Kind regards,
> Pavel
> 
> 
> 2017-11-01 16:46 GMT+01:00 Scott Harvanek <scott.harvanek at login.com <mailto:scott.harvanek at login.com>>:
> Adam,
> 
> I thought that the MPC3E and MPC5E had the same generation Trio w/ XL and XQ chips?  Just the MPC5E has two XM chips.
> 
> Scott H
> 
> 
> 
> > On Nov 1, 2017, at 10:28 AM, <adamv0025 at netconsultings.com <mailto:adamv0025 at netconsultings.com>> <adamv0025 at netconsultings.com <mailto:adamv0025 at netconsultings.com>> wrote:
> >
> >> Scott Harvanek
> >> Sent: Tuesday, October 31, 2017 6:57 PM
> >>
> >> Hey folks,
> >>
> >> We have some MX480s we need to add queuing capable 10G/40G ports to
> >> and it looks like MPC5EQ-40G10G is going to be our most cost effective
> >> solution.  Has anyone run into any limitations with these MPCs that aren’t
> >> clearly documented?
> >>
> >> We intend to use them for L3/VLAN traffic w/ CoS/Shaping.  Currently we’re
> >> doing that on MPC2E NG Qs w/ 10XGE-SFPP MICs , any reason we couldn’t
> >> do the same on this along with the adding of the 40G ports? Any Layer3
> >> limitations or the normal 2MM/6MM FIB/RIB?
> >>
> > Hey Scott,
> > I'd rather go with a standard Trio architecture i.e. one lookup block one buffering block (and one queuing block) -so mpc3 or mpc7.
> > To me it seems like 4 and 5 are just experiments with the Trio architecture that did not stood the test of time.
> >
> > adam
> >
> >
> 
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