[j-nsp] MPC7 / QSFP28 I2C issue

[Theo Voss]

Hi all,

we’re experiencing a strange issue on MPC7, configured for 2x40G 4x100G. On two different routers, two different QSFP28 (not same PIC/Port) ports on MPC7 do not recognize the inserted 100G LR4 transceiver while showing I2C errors. We’ve already exchanged the transceiver and verified that the transceivers are OK. Next step is a PIC and FPC reboot, then JTAC case. Just wanted to check if someone has seen an identical issue?

Model: mx480
Junos: 17.3R3-S1.5

FPC 0            REV 43   750-056519   MPC7E 3D MRATE-12xQSFPP-XGE-XLGE-CGE
  PIC 0                   BUILTIN      BUILTIN           MRATE-6xQSFPP-XGE-XLGE-CGE
    Xcvr 0       850nm    740-032986   QSFP+-40G-SR4
    Xcvr 2       850nm    740-058734   QSFP-100GBASE-SR4
    Xcvr 5       850nm    740-058734   QSFP-100GBASE-LR4
  PIC 1                   BUILTIN      BUILTIN           MRATE-6xQSFPP-XGE-XLGE-CGE
    Xcvr 0       850nm    740-032986   QSFP+-40G-SR4
    Xcvr 2                NON-JNPR     QSFP-100GE-DWDM2
    Xcvr 5                NON-JNPR     UNKNOWN *** AFFECTED ***

Transceiver 0/5 is 3rd party (Flexoptix), we also tried different modules from different production badges.
The DWDM2 is a PAM4 transceiver, which works well on other fully-utilized MPC7 cards.

Dec  6 20:16:40  fpc0 qsfp_tk_eeprom_scanning_check: qsfp-0/1/5 failed scanning eeprom addr 0x0 err 4294967285
Dec  6 20:16:41  fpc0 qsfp_tk_read_los: qsfp-0/1/5: failed to read at reg offset 0x3
Dec  6 20:17:08  fpc0 qsfp_tk_read_los: qsfp-0/1/5: failed to read at reg offset 0x3
Dec  6 20:17:09  fpc0 qsfp-0/1/5: I2C access failures exceeded 10 times, disable periodic. Please re-insert or replace the optics

Thanks,
Theo