> On the VIP4 thing, can you explain what changes are made to increase the
> bandwidth? I recall hearing something about expanding the CyBUS to 64
bits
> by using the 2 16bit channels and the 32 bit channel used by the
> VIP2-50.
You probably talking about "CzBus" since it's has not materialized yet -
one would think that it was canceled.
In any case, it doesn't look like there is a market for faster bus on
7500's - at speeds higher than OC3, one should opt for
a GSR or something.
As far as MIX - "multiservice interchange" or MX enabled chassis on 7500 -
this is just to provide a
"TDM functionality" to crossconnect DS0's between MIX enabled cards or
PA's - there are MIX enabled
PA's for VXR's, but I haven't seen any MIX enabled VIP's yet - I am coming
to the same conclusions as above ;-)
> I also am aware of the PCI enhancements to
> increase throughput to 800 Mbps (I assume 400/PA). There isn't much in
the
> docs on this, and if need be I can get it from the account team, but I
> figured you may have something fast off the top of your head... ;-)
As far as I understand there are two totally separate PCI buses on VIP4 so
PCI buses 1 and 2 are no longer bridged to PCI bus 0 like on VIP2.
Also, I am guessing, that each PCI bus can operate at 33 Mhz or 66 Mhz (
PCI rev 2.1 specs ) -
this is the only way to get more bw here (64 bit wide PCI bus would require
bigger connector and it is not there on VIP4 - I checked ;-)),
so combined with a PA that supports faster PCI bus clock rate (like OC12 or
GigE+ and only single PA per VIP4 of course)
it could theoretically push up to 800 Mbps or more. But again, CyBus would
be a limiting factor here.
Would be nice to hear from folks at cisco if the above assumptions are
correct.
Regards,
Mike.
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