Re: [nsp] [nsp] RSP8 amd Rec. Side Buffering (was: VIP if-con and IOS switching)

From: Siva Valliappan (svalliap@cisco.com)
Date: Wed May 30 2001 - 05:02:34 EDT


comments below -

>
> As far as I understand there are two totally separate PCI buses on VIP4 so
> PCI buses 1 and 2 are no longer bridged to PCI bus 0 like on VIP2.
> Also, I am guessing, that each PCI bus can operate at 33 Mhz or 66 Mhz (
> PCI rev 2.1 specs ) -
> this is the only way to get more bw here (64 bit wide PCI bus would require
> bigger connector and it is not there on VIP4 - I checked ;-)),
> so combined with a PA that supports faster PCI bus clock rate (like OC12 or
> GigE+ and only single PA per VIP4 of course)
> it could theoretically push up to 800 Mbps or more. But again, CyBus would
> be a limiting factor here.

correct. it's a dual 32 bit PCI bus. and it can operate at
different speeds - which gives you the performance enhancements.

regards
.siva



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