[nsp] E3 with both CSUs as clock master?

[Bulger, Tim]

Not specifically Cisco related, but was hoping that someone could
provide some insight into an unusual problem.  I have an E3 circuit
which will only stay stable and error free if both CSUs are set as clock
master..  This goes against everything I have read and seen in the past
with T3s.  Does anyone have any ideas?  Should I just be happy that it's
up and not worry about it? :)

Thanks,
Tim