[nsp] E3 with both CSUs as clock master?

[warner at cats.ucsc.edu]

>Not specifically Cisco related, but was hoping that someone could
>provide some insight into an unusual problem.  I have an E3 circuit
>which will only stay stable and error free if both CSUs are set as clock
>master..  This goes against everything I have read and seen in the past
>with T3s.  Does anyone have any ideas?  Should I just be happy that it's
>up and not worry about it? :)

In data applications, setting both sides to use their own internal
clock for xmit works OK.  That's because there is no problem if
north and south run at different rates.  What you'll find, however,
is that you can't do an error-free loop test.  When the loopback
relay closes, whatever small difference there is in the frequency
will cause slips to occur.  Creating a situation that is guaranteed
to fail certain tests even when nothing is wrong can be confusing.
In my understanding, that's the biggest problem.

-jim warner,  UCSC