[c-nsp] %SYS-4-CONFIG_NEWER: Configuration from version 12.3 maynot be correctly understood

[Yucel Guven]

The version of IOS image in the flash may be different from the image in the bootstrap.
No need to worry about it, BUT always double check your configuration especially 
the interface configurations :)
 
-yucel

	-----Original Message----- 
	From: elliot moore [mailto:nsp at devnull.org.uk] 
	Sent: Thu 9/2/2004 6:02 PM 
	To: cisco-nsp at puck.nether.net 
	Cc: 
	Subject: [c-nsp] %SYS-4-CONFIG_NEWER: Configuration from version 12.3 maynot be correctly understood
	
	

	Hello list, sorry I tried to search for this, but got an 404 error from
	http://puck.nether.net/cgi-bin/htsearch
	
	My question:
	I have taken ownership of a 7204VXR NPE400
	
	But at boot I get the message:
	%SYS-4-CONFIG_NEWER: Configuration from version 12.3 may not be
	correctly understood
	%SYS-6-BOOT_MESSAGES: Messages above this line are from the boot loader.
	
	The config is empty/reset/defaults
	My IOS IS 12.3 - is this conflicting with the Bootstrap?
	Should this be happening, this does not look correct, is it safe to
	proceed?
	
	e.
	
	
	
	Router#sh ver
	Cisco Internetwork Operating System Software
	IOS (tm) 7200 Software (C7200-IS-M), Version 12.3(5a), RELEASE SOFTWARE
	(fc1)
	Copyright (c) 1986-2003 by cisco Systems, Inc.
	Compiled Mon 24-Nov-03 21:24 by kellythw
	Image text-base: 0x60008AF4, data-base: 0x61C1A000
	
	ROM: System Bootstrap, Version 12.2(4r)B2, RELEASE SOFTWARE (fc2)
	BOOTLDR: 7200 Software (C7200-KBOOT-M), Version 12.1(8a)E, EARLY
	DEPLOYMENT RELEASE SOFTWARE (fc1)
	
	Router uptime is 3 minutes
	System returned to ROM by reload at 15:48:47 UTC Thu Sep 2 2004
	System image file is "disk0:c7200-is-mz.123-5a.bin"
	Last reload reason: Reload command
	
	
	cisco 7204VXR (NPE400) processor (revision A) with 114688K/16384K bytes
	of memory.
	Processor board ID 23685273
	R7000 CPU at 350MHz, Implementation 39, Rev 3.3, 256KB L2, 4096KB L3
	Cache
	4 slot VXR midplane, Version 2.3
	
	Last reset from power-on
	Bridging software.
	X.25 software, Version 3.0.0.
	
	PCI bus mb0_mb1 has 400 bandwidth points
	PCI bus mb2 has 400 bandwidth points
	
	4 FastEthernet/IEEE 802.3 interface(s)
	125K bytes of non-volatile configuration memory.
	
	47040K bytes of ATA PCMCIA card at slot 0 (Sector size 512 bytes).
	8192K bytes of Flash internal SIMM (Sector size 256K).
	Configuration register is 0x2102
	
	
	
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