[c-nsp] Cisco ISR T3

[sthaug at nethelp.no]

>   afaik, there is lot of buffering overhead associated with eth frame <->
> atm cell conversion, and that buffering has to be done by the cpu.

What on earth are you talking about here? Segmentation and reassembly
is done in hardware (by the SAR chip) on any reasonably modern ATM
chipset. The amount of buffering needed for a 1500 byte packet arriving
on an ATM (or E3/T3/OC3) port is the same as the amount of buffering
needed for a 1500 byte packet arriving on an Ethernet port (there are
some differences in encapsulation, of course).

Steinar Haug, Nethelp consulting, sthaug at nethelp.no