[c-nsp] ME3400 Transmit queues and architecture

[ML]

This is a multi part question please bear with me.

Background synopsis: A large (on the order of millions) of output queue 
drops were causing noticeable breakup of multicast video streams.
I learned that the default egress queue size is 160 starting in 
12.2.46SE.  I upgraded some lab switches, This helped my situation 
immensely.
However output queue drops continued albeit much less frequently.

Question 1:
 From an off-list reply to my original question I was told I could 
increase the number of queues per interface with this policy-map:

policy-map max-queue
  class class-default
  queue-limit 544

Naturally I would want to apply to this to every interface, however I am 
unsure if this will be detrimental.  What I don't know is where queue 
space exists: DRAM, a small supply of onboard SRAM?
If I allocate 544 queues to every interface on an ME3400-24TS-A will I 
starve other processes for memory (unlikely check my math below)?
If the current default queue size is 160 and I increase it to 544 for 
all FastEthernet interfaces I would increase the amount of memory usage 
by 2.25 megabytes:

Queue size is 256 bytes; 24 interfaces.
((256*(544-160)bytes))*24 = 2.25 megabytes

Since these ME3400s are just access switches I seem to always at least 
50MB of free memory. Therefore 2.25 MBs doesn't seem like a big impact.

Am I correct in my calculations about the impact of the preceding 
policy-map applied system wide? Do the output queues live in run of the 
mill DRAM?


Question 2:

When I do apply the 'max-queue' policy-map to an interface and inspect 
my work:

sh platform qos debug port-class
sh platform qos debug port-config X

Port Class 0: Queue #3 seems to have my new max-queue setting but every 
other Port Class  and corresponding  Queue are still set to 48 (The 
pre-12.2.46SE default queue size?)

Am I missing something when I use these commands? This is new territory 
for me.


Question 3:

Are the FastEthernet ports on the ME3400 over subscribed in any way? Can 
I expect line-rate performance on every port at once or is there an ASIC 
handling groups of 2^n ports?


Thanks in advance for any help.

****