[c-nsp] Cisco Switch Packet Buffering Matrix?

[Jeff Kell]

To dredge up an old thread one more time.... as I am still looking for
answers...

2950 data sheets state (in summary, the details are scattered throughout
the document)

*2950SX-48 *13.6Gbps backplane, 10.1Mpps forwarding, 16Mb DRAM, "8 MB
packet buffer memory architecture shared by all ports"

3550 data sheets state similarly

*3550-48 *13.6Gbps backplane, 10.1Mpps forwarding, 64Mb DRAM, "4 MB
memory architecture shared by all ports"  (only 2Mb for 24-port models)

The 2960/3560 make no mention of packet buffer arrangement or depth.

But I'm somewhat surprised that the 2950 has as much as 4x the depth of
the 3550 in terms of packet buffering(!).  Is this indeed the case?  or
a marketing misdirection?

Anyone have any clues as to the 2960/3560 relative placement?

Jeff