[c-nsp] Cisco Switch Packet Buffering Matrix?

[Marian Ďurkovič]

On Wed, Jun 02, 2010 at 10:53:08AM -0400, Jeff Kell wrote:
> *2950SX-48 *13.6Gbps backplane, 10.1Mpps forwarding, 16Mb DRAM, "8 MB
> packet buffer memory architecture shared by all ports"
> 
> *3550-48 *13.6Gbps backplane, 10.1Mpps forwarding, 64Mb DRAM, "4 MB
> memory architecture shared by all ports"  (only 2Mb for 24-port models)
> 
> The 2960/3560 make no mention of packet buffer arrangement or depth.
> 
> But I'm somewhat surprised that the 2950 has as much as 4x the depth of
> the 3550 in terms of packet buffering(!).

Don't be. The newer switches have even less...

*2960G - only 384 kB per ASIC - i.e. 8 GE (!) ports.

   M.