[c-nsp] ME3600X architecture

[Jeff Bacon]

Primarily a question for Waris probably: 

Is there anything out there about the "Carrier Ethernet ASIC" or the overall architecture of the box?

Looking at the board itself, it looks as though there's two separate but identical ASIC complexes on the board. My instinct says that the 10G ports are run by one ASIC and the 24 1G ports are run by the other ASIC, with some sort of bridge or bus between 'em. 

I only just got my hands on one (and yes of course I ripped it apart) so I'm only just starting to answer questions - but there's so many nice docs on the 6500 and 4900s that I'm spoiled... 

Thanks! 
-bacon