[c-nsp] Fabricpath and L3 on the same line card

[Chris Evans]

Okay great, that is what I thought.. Seems like a simple feature to miss.

Do you know if there are any performance limitations with it? Like could
internal ports be burned for routing efforts? It seems that many companies
have problems with the TRILL header and can't do SVI natively like we can
today. How these chips can handle MPLS, GRE, and other headers with no
issues and not TRILL is interesting to me.


On Thu, Mar 21, 2013 at 1:02 PM, Lustgraaf, Paul J [ITNET] <
grpjl at iastate.edu> wrote:

> Well, I'm doing it, so I guess it can.
>
> And F2 modules must be in a VDC by themselves, so no M1 could possibly be
> involved.
>
> Paul Lustgraaf                    grpjl at iastate.edu
>  "Change is inevitable.  Progress is not."
> Network Engineer, Iowa State University IT Services
>                                515-294-0324
>
>
> -----Original Message-----
> From: cisco-nsp-bounces at puck.nether.net [mailto:
> cisco-nsp-bounces at puck.nether.net] On Behalf Of Chris Evans
> Sent: Thursday, March 21, 2013 11:57 AM
> To: cisco-nsp
> Subject: [c-nsp] Fabricpath and L3 on the same line card
>
> Can anyone tell me if Cisco F2/F2e line modules can run Fabricpath and L3
> (SVI's) on the same line module. Is it line rate as well or does it proxy
> through an ASIC burning ports, etc. Is an M1 module required?
>
> Someone has told me it cannot, but I believe it can. Are there any
> limitations with it?
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