[c-nsp] Route processor memory at 99% on 720-3bxl

Mack McBride mack.mcbride at viawest.com
Wed Jun 22 17:23:11 EDT 2016

The BGP process does receive the updates.  It also has its own version of the RIB.
The IP RIB Update process handles the 'installed routes' and pushes things out to the CEF.

Mack McBride | Senior Network Architect | ViaWest, Inc.
O: 720.891.2502 | C: 303.720.2711 | mack.mcbride at viawest.com | www.viawest.com

-----Original Message-----
From: Mark Tinka [mailto:mark.tinka at seacom.mu]
Sent: Wednesday, June 22, 2016 1:35 PM
To: Mack McBride; chiel; cisco-nsp at puck.nether.net
Subject: Re: [c-nsp] Route processor memory at 99% on 720-3bxl

On 22/Jun/16 19:32, Mack McBride wrote:

> My understanding is that on the 6500/7600 series the IP RIB Update process also contains the prebuilt FIB to be pushed into CEF.
> I may be wrong on that but I don't think so.  BGP-SD definitely does not push the routes into the IP RIB Update process.

You can't stop the control plane from receiving the routes once they have arrived. But you can stop the data plane from doing so.

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