[c-nsp] Cisco and microbursts

[Saku Ytti]

http://www.cisco.com/c/dam/en/us/td/docs/routers/asr920/design/Cisco-ASR920-Microburst-whitepaper.pdf

Pray tell, how will ASIC clock reduce impact of microbursts? I wonder
if during testing they were pacing packets or actually bursting. I
know that for example in IXIA there is no way to test bursting, and
with pacing it looks like you never need any buffers.

Obviously there is no way ASIC can cause variant delay from 11us to
500us, clearly that was caused by buffering.
ME3600X is what 65Mpps box, so that's pretty much only thing we need
to know from ASIC performance POV. Having higher clock ASIC doing same
65Mpps is completely irrelevant.

If 10GE is receiving say 50MB burst of TCP window, there is nothing
higher clock ASIC can do, to help sending it to 1GE, other than store
it in packet buffers.
-- 
  ++ytti