[c-nsp] Cisco and microbursts

Adam Vitkovsky Adam.Vitkovsky at gamma.co.uk
Wed May 18 12:44:31 EDT 2016


> Saku Ytti
> Sent: Friday, May 13, 2016 5:42 PM
>
> http://www.cisco.com/c/dam/en/us/td/docs/routers/asr920/design/Cisco-
> ASR920-Microburst-whitepaper.pdf
>
> Pray tell, how will ASIC clock reduce impact of microbursts? I wonder if during
> testing they were pacing packets or actually bursting. I know that for
> example in IXIA there is no way to test bursting, and with pacing it looks like
> you never need any buffers.
>
> Obviously there is no way ASIC can cause variant delay from 11us to 500us,
> clearly that was caused by buffering.
> ME3600X is what 65Mpps box, so that's pretty much only thing we need to
> know from ASIC performance POV. Having higher clock ASIC doing same
> 65Mpps is completely irrelevant.
>
> If 10GE is receiving say 50MB burst of TCP window, there is nothing higher
> clock ASIC can do, to help sending it to 1GE, other than store it in packet
> buffers.
> --
I'm not that familiar with these small ASICs -or actually FPGAs (as a crossover between ASIC and NPU).
But since in FPGAs not everything is programed in HW (I'm guessing), wouldn't the execution time be partly dependent on what features are enabled? So then higher clock-rate would mean that you can execute more instructions per given Tc. That is to be able to do more advanced stuff while sustaining the nominal pps rate?
Just thinking out loud.


adam










        Adam Vitkovsky
        IP Engineer

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