[c-nsp] Cisco and microbursts

[Gert Doering]

Hi,

On Wed, May 18, 2016 at 04:44:31PM +0000, Adam Vitkovsky wrote:
> I'm not that familiar with these small ASICs -or actually FPGAs (as a crossover between ASIC and NPU).
> But since in FPGAs not everything is programed in HW (I'm guessing), wouldn't the execution time be partly dependent on what features are enabled? So then higher clock-rate would mean that you can execute more instructions per given Tc. That is to be able to do more advanced stuff while sustaining the nominal pps rate?

If you can't get it out of your egress due to "fast burst coming in,
no way to store it for the time being", making the "throw packat away due to
no buffers" *faster* isn't going to help much, right?

Faster CPU will not magically spawn more buffer memory...

gert

-- 
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Gert Doering - Munich, Germany                             gert at greenie.muc.de
fax: +49-89-35655025                        gert at net.informatik.tu-muenchen.de
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