[c-nsp] Cisco and microbursts

[James Jun]

On Wed, May 18, 2016 at 04:44:31PM +0000, Adam Vitkovsky wrote:
> > --
> I'm not that familiar with these small ASICs -or actually FPGAs (as a crossover between ASIC and NPU).
> But since in FPGAs not everything is programed in HW (I'm guessing), wouldn't the execution time be partly dependent on what features are enabled? So then higher clock-rate would mean that you can execute more instructions per given Tc. That is to be able to do more advanced stuff while sustaining the nominal pps rate?
> Just thinking out loud.

Yea, I'm not sure.  No amount of ASIC speed is going to change the interface clock speed to shoot frames off the TxRing.  So not sure how faster ASIC is going to solve 10GE-to-1GE downstep without having any buffer memory.

We had many "issues" with microburst on ASR920 out of the box with longhaul bursty traffic.  Default buffer sizes had to be increased, and 12MB doesn't leave a lot of room for HQoS on top of that, though still manageable.  But still, I'm happy with the platform.

James