[c-nsp] Cisco N540-ACC-SYS ipv4 routes

[James Bensley]

On Mon, 13 Jul 2020 at 08:27, Saku Ytti <saku at ytti.fi> wrote:
>
> On Mon, 13 Jul 2020 at 00:54, Mark Tinka <mark.tinka at seacom.com> wrote:
>
> > The general messaging, over the years, has been that ASIC is quick but
> > not flexible, while NPU is flexible but can get bogged down by added
> > flexibility in time.
>
> The classical view is that packet through ASIC takes constant,
> invariant time, and packet through NPU takes variant time, depending
> on how many instructions the NPU needs to perform for this packet.

It's tough to make a clear line. This is roughly the definition I use
too ^, fixed vs flexible time, with the exception that some ASICs
support packet recirculation meaning overall packet processing time
increased but, technically each pass of the packet is still in fixed
time.


> But if that is a strict definition, then we don't really have ASICs
> outside really cheap switches, as there is some programmability in all
> new stuff being released. So I'm not sure what the correct definition
> is.

I would say that ASICs are fixed function single die or very small
number of tightly bound dies that have a fixed feature set. My
definition of an NPU is a collection of ASICs and/or a collection of
purpose built components, e.g. "a complex of ASICs". NPUs tend to have
a varying feature set depending on what uCode you load on them.
Although some ASICs have limited flexibility based on the uCode you
load on them, the features are more or less restricted to the burnt in
features, whereas an NPU could support radically different features
throughout their lifetime.


> Equally when does a software router become a hardware router? Why is
> XEON not NPU but Trio is? Are there some objective facts which
> differentiate CPU from NPU and NPU from ASIC?

Added inline..

> # NPU vs CPU?
> - NPU tends to have more cores than CPU
> - NPU has application specific instruction set
> - NPU has application specific memory interface
- NPUs (Trio from Juniper MX, NP3C from Cisco 7600,
Trident/Typhoon/Tomahawk from Cisco ASR9) are all *collections* of
components/chips working together (ASICs, S/D/RLD-RAM, e/i-TCAM, TOPs,
ALUs, FPGAs, CPLDs).
 - CPU is more general purpose, that is why we have GPUs + GDDR for
example, to address a specific purpose the CPU is not geared towards,
equally we have NPUs to address another purpose a CPU is not geared
towards.
- CPUs are often multiple components too (processor(s), i/d-caches,
ALUs) but running generic code with a generic instruction set. The
components in the NPU run a limited and purpose specific instruction
set with a very different design (e.g. highly parallelised as you
said).

> # NPU vs ASIC?
> - ASIC does parsing and lookup in silicon, not by running a set of
> instruction given by a program
> - ASIC is constant time, NPU is variable time
> - ASIC has many type of silicons for different function, NPU has many
> identical siicons running different set of instruction depending on
> packet/config
- NPUs also have function specific silicon too e.g. TOPs (Task
Optimised Processors) which exist in ASR9K NPUs, but not in Trio, but
they also run uCode and have a very small amount of flexibility.

Cheers,
James.