[c-nsp] Cisco N540-ACC-SYS ipv4 routes

[adamv0025 at netconsultings.com]

Hi James,

> James Bensley
> Sent: Thursday, July 16, 2020 9:25 AM
> 
> The
> PFC3 cards on 7600 require a collection of ASICs (one to connect to the
front
> panel ports, one for queueing, one for forwarding lookups and rewrites,
one
> for backplane / crossbar transmission and reception etc.), so whilst they
> probably don't fit a strict definition of NPU I think they are in the
interest in-
> between stage of evolving from single ASIC -> a bunch of loosely coupled
> ASICs
> -> a complex of tightly bound ASIC.
Which is indeed how all the modern NPUs are actually built. 
As the lithography shrinks more and more of these components are placed
under one roof but inside it's still a collection of distinct functional
blocks.
But out of those around two dozens of high level functional blocks a typical
NPU architecture has, in discussions around comparison between ASICs and
NPUs, I think the only part/ functional block worth focusing on is the one
responsible for the packet header (or in some cases the whole packet)
processing and specifically the flexibility that the particular functional
block provides in terms of possible operations on the packet header. 
There we could then spot a certain pattern where functional blocks
responsible for packet header processing operating with less flexibility
tend to provide more consistent pps performances while costing less, in
contrast to those operating with more flexibility but expressing more
variability in pps performance while costing more. Then we can discuss
whether we want to call the former ACICs and the later NPUs but that's just
a nomenclature. 
     
adam