[j-nsp] SRX hardware acceleration caveats

[Phil Mayers]

On 17/06/12 08:14, Saku Ytti wrote:

> This is true for branch (multicore cavium octeon). But not for
> 1k/3k/5k. And there is no where to offload in branch.

This is interesting. I was not aware of the EZchip offload in the 
high-end stuff.

Can anyone comment on the expected (or observed) differences in latency 
& jitter when using EZchip offload? Does it lead to theoretically higher 
throughput (bytes or packets)?

Also, I note from the docs that the EZchip does limited TCP sequence 
inspection of 64k (times whatever the window scaling is). Might this 
lead to problems with large bandwidth*delay flows?

The absence of IPv6 & fan-out multicast is a real pain though...