[j-nsp] SRX hardware acceleration caveats

Pavel Lunin plunin at senetsy.ru
Mon Jun 18 07:24:37 EDT 2012

Previous message: [j-nsp] SRX hardware acceleration caveats
Next message: [j-nsp] SRX hardware acceleration caveats
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

18.06.2012 15:22, Pavel Lunin wrote:
> easily pass a single 10G interface (and, consequently, NPC).
NPU, to be precise.

Previous message: [j-nsp] SRX hardware acceleration caveats
Next message: [j-nsp] SRX hardware acceleration caveats
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the juniper-nsp mailing list